1. Technical Field
The present invention relates generally to an improved data processing system and in particular to a method and apparatus for processing data. Still more particularly, the invention relates to an efficient muxing scheme to allow for bypass and array access in memory arrays.
2. Description of Related Art
In modern data processing systems, data is read from and stored into arrays of memory cells. One type of memory is a cache, which serves as temporary memory for recently used data. In addition, data is stored in collections referred to as pages. Page sizes are typically about four kilobytes, though a page may vary in size from a few bytes to several megabytes. Thus, pages of data are read from and stored into caches of one or more arrays of memory cells.
In certain array designs, bypassing an array and forwarding data is often needed when data flows from other components of a data processing system. Bypassed data is forwarded to an output before writing to the array. Depending on the page size, certain bits accessed from an array are bypassed rather than using the read values of the array. For example, for large pages, only certain data is read and the rest of the data may bypass the array. Thus, while managing data flow in a data processing system, the data processing system supports read access to the array, bypassing of data past the array, and bypassing of some data past the array based on page size. These three functions may be referred to as read access, data bypass, and page size bypass.
For example, if a page contains ten bits of information, a read access operation causes all ten bits of information to be read from an array. In a data bypass operation, all ten bits of information skip the array and are bypassed directly to an output. In an exemplary page size bypass operation, two of the ten bits are bypassed and the other eight bits are read. The two bits are bypassed because those bits need not be read.
In order to support read access, data bypass, and page size bypass, a three to one multiplexer (3:1 MUX) is required for prior art arrays. However, a 3:1 MUX requires relatively complex control circuitry and requires more physical space to implement on hardware. Thus, it is desirable to reduce the complexity of the MUX and implement a two to one MUX (2:1 MUX).